 | Resume: Sr Mechanical Engineer Little Canada, MN US SUMMARY OF QUALIFICATIONS: Senior engineering professional with more than 25 years of functional experience providing engineering solutions for product designs, documentation processes, and presenting design reviews to customers and internal management. I have acquired an extensive background in medical devices and their technologies. Also strong, in manufacturing, and industrial environments in planning and executing design strategies. Engineering Summary • Project engineering leadership • | | | | |
 | Job: Digital ASIC Design Engineer - Low Power Cambridge, MA US We are NextWave Wireless. An exciting company with a clear vision. At NextWave, we are actively developing many of the enabling wireless technologies and products needed to ... NextWave Wireless | | | | |
 | Resume: Entry Level full time job San Jose, CA US SUMMARY Entry-level computer engineer with expert skills in VLSI Design, verification and object oriented design OBJECTIVE: To seek a challenging full-time opportunity as a VLSI Engineer in verification, design and Testing EDUCATION | | | | |
 | Web: ASIC Design Jobs on CareerBuilder.com ASIC Design Jobs on CareerBuilder.comAustin, TX Digital ASIC Design Engineer using Verilog View full job description Save to MyCareerBuilder Saved Job (View Saved Jobs) Email to a friend | | | | |
 | Resume: Management/Leadership Development Training Professional Raleigh, nc US OBJECTIVE Senior-level position drawing upon demonstrated strengths in quality program leadership, engineering, training program development and implementation, project management, cross-functional team leadership, problem solving, and proven results. Demonstrated ability to manage teams and large projects at all organizational levels to successful completion. QUALIFICATIONS Highly-motivated, results-oriented professional with 18 years of progressive assignments in Designing and Delive | | | | |
 | Job: Sr. Hardware - Test Engineer Tustin, CA US Sr. Hardware / Test EngineerLocation: Tustin, CAGÇó Forza Silicon is a privately held mixed signal chip design and fablesssemiconductor company creating breakthrough designs and products for worldclasscustomers. ... Forza Silicon Corporation | | | | |
 | Job: Sr. Video Processor ASIC Design Engineer Sunnyvale, CA US Sr. Video Processor ASIC Design EngineerLocation: Sunnyvale, CaliforniaDescription:Experience: 5-10 years experience in video processor ASIC design Overview:OmniVision, a leading independent supplier ... OmniVision Technologies | | | | |
 | Job: Asic Design Engineer Milpitas, CA US Sigma Designs specializes in silicon-based MPEG decoding for streaming video, progressive DVD playback and advanced digital set-top boxes. Sigma ... Sigma Designs, Inc. | | | | |
 | Web: Asic verification jobs - SOCcentral-Jobs style="margin-left:2.5em"Asic verification jobs - SOCcentral-JobsJul 03, Principal FPGA/ASIC Design Engineer, Hireworks Staffing, Andover, MA . Jun 26, ASIC Design Engineer, Servsolid, Germantown, MD | | | | |
 | Resume: Engineer Fremont, 94 US OBJECTIVE Seeking a challenging position as an Engineer, where I can use my skills towards the betterment of the firm. PROFILE Currently, Internship at UMC’s IP Design Group. Excellent knowledge at ASIC, FPGA & Analog /Mixed-Signal Design Flow. Very Good understanding to write Verilog RTL codes. Very Good scripting/programming experience in Unix Shell Script, Perl, C/C++ & Java. Strong Skills of using EDA Front/Back End Tools. Currently, assisting as a Teaching Assistant of Place & | | | | |
 | Resume: DSP, ASIC Mississauga, Ontario CA EDUCATION MSc, IC Digital Electronic Circuit Design using the state-of-art Field Programmable Gate Array (FPGA), Cairo University, Faculty of Engineering, Aug 1995 BSEE, with Major of Electronics and Telecommunication, Cairo University, faculty of Engineering, July 1990 PhD, with the major of VLSI design in DSP algorithm, Concordia university of Montreal, faculty of engineering, Canada 2000- 2003 (currently on hold). P. Eng. designated (Professional Engineering of | | | | |
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